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Freescale Semiconductor Technical Data
MC100ES6220 Rev 4, 04/2005
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
The MC100ES6220 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6220 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * * * Two independent 1:10 differential clock fanout buffers 130 ps maximum device skew SiGe technology Supports DC to 1 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL compatible differential clock inputs Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply Standard 52-lead LQFP package with exposed pad for enhanced thermal characteristics Supports industrial temperature range Pin and function compatible to the MC100EP220 52-lead Pb-free Package Available
MC100ES6220
LOW VOLTAGE DUAL 1:10 DIFFERENTIAL ECL/PECL CLOCK FANOUT BUFFER
TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A-01
Functional Description
AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 1336A-01
The MC100ES6220 is designed for low skew clock distribution systems and supports clock frequencies up to 1 GHz. The device consists of two independent clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6220 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the MC100EP220.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
QB0
QB1 QB1
Fanout Buffer A VCC
CLKA CLKA
QA0 QA0 QA1 QA1
VCC QA5 QA5 QA4 QA4 QA3 QA3 QA2 QA2 QA1 QA1 QA0 QA0
39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 41 42 43 44 45 46 47 48 49 50 51 52 1 VCC 2 VCC 3 VEE 4 CLKA 5 6 7 CLKB 8 25 24 23 22
QA9 QB0
QA6
QA6
QA7
QA7
QA8
QA8
QA9
VCC
QB2 QB2 QB3 QB3 QB4 QB4 QB5 QB5 QB6 QB6 QB7 QB7 VCC
VEE
QA8 QA8 QA9 QA9 QB0 QB0 QB1 QB1
MC100ES6220
21 20 19 18 17 16 15
Fanout Buffer B VCC
CLKB CLKB
VEE
QB8 QB8 QB9 QB9
14 9 10 11 12 13 QB9 QB9 QB8 QB8
CLKA VBB
VBB
Figure 1. MC100ES6220 Logic Diagram Table 1. Pin Configuration
Pin CLKA, CLKA CLKB, CLKB QA[0-9], QA[0-9] QB[0-9], QB[0-9] VEE(1) VCC VBB Input Input Output Output Supply Supply Output DC I/O Type ECL/PECL ECL/PECL ECL/PECL ECL/PECL
Figure 2. 52-Lead Package Pinout (Top View)
Function Differential reference clock signal input for fanout buffer A Differential reference clock signal input for fanout buffer B Differential clock outputs of fanout buffer A Differential clock outputs of fanout buffer B Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Reference voltage output for single ended ECL and PECL operation
1. In ECL mode (negative power supply mode), VEE is either -3.3 V or -2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC).
MC100ES6220 2 Advanced Clock Drivers Devices Freescale Semiconductor
CLKB VEE
Table 2. Absolute Maximum Ratings(1)
Symbol VCC VIN VOUT IIN IOUT TS TFUNC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Functional Temperature Range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V mA mA C C Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 3. General Specifications
Symbol VTT MM HBM CDM LU CIN JA,JC, JB TJ Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Input Capacitance Thermal Resistance (junction-to-ambient, junction-to-board, junction-to-case) Operating Junction Temperature(2) (continuous operation) MTBF = 9.1 years 200 4000 2000 200 4.0 See Table 8. Thermal Resistance 0 110 Min Typ VCC - 2(1) Max Unit V V V V mA pF C/W C Inputs Condition
1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6220 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6220 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 3
Table 4. PECL DC Characteristics (VCC = 2.5 V 5% or VCC = 3.3 V 5%, VEE = GND, TJ = 0C to +110C)
Symbol Characteristics Differential Input Voltage(1) Differential Cross Point Input Current(1) Voltage(2) Min Typ Max Unit Condition Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals) VPP VCMR IIN VIH VIL IIN VOH VOL IEE(5) VBB 0.1 1.0 1.3 VCC - 0.3 150 V V A Differential operation Differential operation VIN = VIL or VIN = VIH
Clock Inputs (PECL single ended signals) Input Voltage High Input Voltage Low Input Current(3) VCC - 1.165 VCC - 1.810 VCC - 0.880 VCC - 1.475 150 V V A VIN = VIL or VIN = VIH IOH = -30 mA(4) IOL = -5 mA(4) VEE pins IBB = 0.3 mA
PECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9) Output High Voltage Output Low Voltage VCC - 1.1 VCC - 1.9 VCC - 1.005 VCC - 1.705 80 VCC - 1.42 VCC - 0.7 VCC - 1.4 130 VCC - 1.20 V V
Supply current and VBB Maximum Quiescent Supply Current without Output Termination Current Output Reference Voltage mA V
1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Input have internal pullup/pulldown resistors which affect the input current. 4. Termination 50 to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT) / Rload + (VOL - V TT) /Rload + IEE.
Table 5. ECL DC Characteristics (VEE = -2.5 V 5% or VEE = -3.3 V 5%, VCC = GND, TJ = 0C to +110C)
Symbol Characteristics Differential Input Voltage(1) Differential Cross Point Voltage Input Current(1)
(2)
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) VPP VCMR IIN VIH VIL IIN VOH VOL IEE(5) VBB 0.1 VEE + 1.0 1.3 -0.3 150 V V A Differential operation Differential operation VIN = VIL or VIN = VIH
Clock Inputs (ECL single ended signals) Input Voltage High Input Voltage Low Input Current(3) -1.165 -1.810 -0.880 -1.475 150 V V A VIN = VIL or VIN = VIH IOH = -30 mA(4) IOL = -5 mA(4) VEE pins IBB = 0.3 mA
ECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9) Output High Voltage Output Low Voltage -1.1 -1.9 -1.005 -1.705 -0.7 -1.4 V V
Supply Current and VBB Maximum Quiescent Supply Current without Output Termination Current Output Reference Voltage -1.42 80 130 -1.20 mA V
1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Input have internal pullup/pulldown resistors which affect the input current. 4. Termination 50 to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT) / Rload + (VOL - V TT) / Rload + IEE.
MC100ES6220 4 Advanced Clock Drivers Devices Freescale Semiconductor
Table 6. AC Characteristics (ECL: VEE = -3.3 V 5% or VEE = -2.5 V 5%, VCC = GND) or (PECL: VCC = 3.3 V 5% or VCC = 2.5 V 5%, VEE = GND, TJ = 0C to +110C)(1) Symbol
VPP VCMR fCLK tPD VO(P-P) tsk(O) tsk(PP) tJIT(CC) tSK(P) DCO tr, tf
Characteristics
Differential Input Voltage(2) (peak-to-peak) Differential Input Crosspoint Input Frequency Voltage(3) PECL ECL
Min
0.3 1.1 VEE + 1.1 0
Typ
Max
1.3 VCC - 0.3 -0.3 1000
Unit
V V V MHz
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals)
Differential
PECL/ECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9) Propagation Delay CLKx to Qx0-9 Differential Output Voltage (peak-to-peak) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Pulse Skew Output Duty Cycle Output Rise/Fall Time
(4)
285 400 600 60
550
ps mV
Differential
130 200
ps ps ps ps % % ps
Differential Differential
RMS (1)
1 35
fREF < 0.1 GHz fREF < 1.0 GHz
49.65 46.5 50
50 50
50.35 53.5 350
DCREF = 50% DCREF = 50% 20% to 80%
1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Differential Pulse Generator Z = 50
Z = 50
Z = 50
RT = 50 VTT
DUT MC100ES6220
RT = 50 VTT
Figure 3. MC100ES6220 AC Test Reference
CLKN CLKN QX QX
VPP = 0.8 V
VCMR = VCC - 1.3 V
tPD (CLKN to QX)
Figure 4. MC100ES6220 AC Reference Measurement Waveform
MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 5
APPLICATIONS INFORMATION
Understanding the Junction Temperature Range of the MC100ES6220 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6220, the MC100ES6220 is specified, characterized and tested for the junction temperature range of TJ = 0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 17C/W (2s2p board, 200 ft/min airflow, see Table 8) and a typical power consumption of 1049 mW (all outputs terminated 50 ohms to VTT, VCC = 3.3 V, frequency independent), the junction temperature of the MC100ES6220 is approximately TA + 18C, and the minimum ambient temperature in this example case calculates to -18C (the maximum ambient temperature is 92C. See Table 7). Exceeding the minimum junction temperature specification of the MC100ES6220 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6220 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Table 7. Ambient Temperature Ranges (Ptot = 1049 mW)
Rthja (2s2p board) Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 20C/W 18C/W 17C/W 16C/W 15C/W TA, min(1) -21C -19C -18C -17C -16C TA, max 89C 91C 92C 93C 94C
Maintaining Lowest Device Skew The MC100ES6220 guarantees low output-to-output bank skew of 100 ps and a part-to-part skew of max. 200 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6220 is a mixed analog/digital product. The differential architecture of the MC100ES6220 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
VCC 33...100 nF 0.1 nF VCC MC100ES6220
Figure 5. VCC Power Supply Bypass
1. The MC100ES6220 device function is guaranteed from TA = -40C to TJ = 110C.
MC100ES6220 6 Advanced Clock Drivers Devices Freescale Semiconductor
APPLICATIONS INFORMATION
Using the Thermally Enhanced Package of the MC100ES6220 The MC100ES6220 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the lead frame is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES6220 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6220. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6220 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as shown in Figure 6, providing an efficient heat removal path.
all units mm
package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered.
all units mm
0.2
1.0
4.8
0.2
4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern
Figure 7. Recommended Solder Mask Openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 8. Thermal Resistance(1)
ConvectionL FPM RTHJA(2) C/W 20 18 17 16 15 RTHJA(3) C/W 48 47 46 43 41 4(5) 29(6) RTHJC C/W RTHJB(4) C/W
4.8
Natural 100 200 400 800 4.8
1.0
16
Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter
Exposed pad land pattern
Figure 6. Recommended thermal land pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 7 shows a recommend solder mask opening with respect to the recommended 3 x 3 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 7. For the nominal
1. Applicable for a 3 x 3 thermal via array. 2. Junction to ambient, four conductor layer test board (2S2P), per JES51-7 and JESD 51-5. 3. Junction to ambient, single layer test board, per JESD51-3. 4. Junction to board, four conductor layer test board (2S2P) per JESD 51-8. 5. Junction to exposed pad. 6. Junction to top of package.
It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6220 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers.
MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 7
PACKAGE DIMENSIONS
4X
4X 13 TIPS
0.2 H A-B D D
PIN 1 INDEX 1 52 40 39
0.2 C A-B D 7 1.5 1.3 0.05 B 10 6 12 5 6 6 4 X 4 0.20 R 0.08
(0.2) 0 MIN 0.20 R 0.08 0.25
GAUGE PLANE
A
0.20 0.05
0.75 0.45 (1) VIEW AA
7 0
13 14 26
27
X=A, B OR D
5
6 64 10 6 12 4
C L
B B VIEW Y
48X
0.65
H 1.7 MAX
4X
(12)
VIEW AA
52X
8
(0.3)
BASE METAL
0.1 C 8 J C
SEATING PLANE
0.40 52X 0.22 5 M C A-B D 0.08
4X (12)
J
PLATING
0.20 0.09 0.35 0.20 SECTION B-B
0.16 0.07
8
8
4.78 4.58
4.78 4.58
EXPOSED PAD VIEW Y
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSION TO BE DETERMINED AT SEATING PLANE C. 5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 mm. 6. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. THIS DIMENSION IS MAXIMUM PLSTIC BODY SIZE DIMENSION INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.
VIEW J-J
CASE 1336A-01 ISSUE O 52-LEAD LQFP PACKAGE
MC100ES6220 8 Advanced Clock Drivers Devices Freescale Semiconductor
NOTES
MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 9
NOTES
MC100ES6220 10 Advanced Clock Drivers Devices Freescale Semiconductor
NOTES
MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 11
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MC100ES6220 Rev. 4 04/2005

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